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FiberCOMM / PSTR17R5B

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ngc2edif.log 590 Bytes
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FiberCOMM 提交于 2020-10-21 15:48 . 1.增益控制改为DS3502芯片
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design F:/PSTR17R5B/ipcore_dir/myicon.ngc ...
WARNING:NetListWriters:298 - No output is written to myicon..xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus U0/U_ICON/iCORE_ID_SEL<15 : 0> on block
myicon is not reconstructed, because there are some missing bus signals.
finished :Prep
Writing EDIF netlist file syntmp/myicon..ndf ...
ngc2edif: Total memory usage is 4318260 kilobytes
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https://gitee.com/fibercomm/PSTR17R5B.git
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