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Flow report for MY_DDS_PRO
Thu Nov 16 21:04:41 2023
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+----------------------------------------------+
; Flow Status ; Successful - Thu Nov 16 21:04:41 2023 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; MY_DDS_PRO ;
; Top-level Entity Name ; MY_DDS_PRO ;
; Family ; MAX II ;
; Device ; EPM1270T144C5 ;
; Timing Models ; Final ;
; Met timing requirements ; No ;
; Total logic elements ; 910 / 1,270 ( 72 % ) ;
; Total pins ; 49 / 116 ( 42 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 11/16/2023 21:04:23 ;
; Main task ; Compilation ;
; Revision Name ; MY_DDS_PRO ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+----------------------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+----------------------------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 127872478721258.170013986323056 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; D:/Quartus_project/Verilog/DDS/MY_DDS_PRO/MY_DDS_PRO.dpf ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+---------------------------------------+----------------------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 227 MB ; 00:00:03 ;
; Fitter ; 00:00:05 ; 1.0 ; 236 MB ; 00:00:06 ;
; Assembler ; 00:00:00 ; 1.0 ; 202 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 173 MB ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 184 MB ; 00:00:01 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:12 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; LAPTOP-B0KVNAVN ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; LAPTOP-B0KVNAVN ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; LAPTOP-B0KVNAVN ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; LAPTOP-B0KVNAVN ; Windows Vista ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; LAPTOP-B0KVNAVN ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
quartus_fit --read_settings_files=off --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
quartus_asm --read_settings_files=off --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
quartus_tan --read_settings_files=off --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
quartus_eda --read_settings_files=off --write_settings_files=off MY_DDS_PRO -c MY_DDS_PRO
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