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From 7f9f1dd3c87cffeab58150997e22e8fff707646b Mon Sep 17 00:00:00 2001
From: Lulu Cheng <chenglulu@loongson.cn>
Date: Mon, 26 Sep 2022 09:42:51 +0800
Subject: [PATCH 019/124] LoongArch: Libitm add LoongArch support.
Co-Authored-By: Yang Yujie <yangyujie@loongson.cn>
libitm/ChangeLog:
* configure.tgt: Add loongarch support.
* config/loongarch/asm.h: New file.
* config/loongarch/sjlj.S: New file.
* config/loongarch/target.h: New file.
Signed-off-by: Peng Fan <fanpeng@loongson.cn>
Signed-off-by: ticat_fp <fanpeng@loongson.cn>
---
libitm/config/loongarch/asm.h | 54 +++++++++++++
libitm/config/loongarch/sjlj.S | 127 +++++++++++++++++++++++++++++++
libitm/config/loongarch/target.h | 50 ++++++++++++
libitm/configure.tgt | 2 +
4 files changed, 233 insertions(+)
create mode 100644 libitm/config/loongarch/asm.h
create mode 100644 libitm/config/loongarch/sjlj.S
create mode 100644 libitm/config/loongarch/target.h
diff --git a/libitm/config/loongarch/asm.h b/libitm/config/loongarch/asm.h
new file mode 100644
index 000000000..a8e3304bb
--- /dev/null
+++ b/libitm/config/loongarch/asm.h
@@ -0,0 +1,54 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ Contributed by Loongson Co. Ltd.
+
+ This file is part of the GNU Transactional Memory Library (libitm).
+
+ Libitm is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _LA_ASM_H
+#define _LA_ASM_H
+
+#if defined(__loongarch_lp64)
+# define GPR_L ld.d
+# define GPR_S st.d
+# define SZ_GPR 8
+# define ADDSP(si) addi.d $sp, $sp, si
+#elif defined(__loongarch64_ilp32)
+# define GPR_L ld.w
+# define GPR_S st.w
+# define SZ_GPR 4
+# define ADDSP(si) addi.w $sp, $sp, si
+#else
+# error Unsupported GPR size (must be 64-bit or 32-bit).
+#endif
+
+#if defined(__loongarch_double_float)
+# define FPR_L fld.d
+# define FPR_S fst.d
+# define SZ_FPR 8
+#elif defined(__loongarch_single_float)
+# define FPR_L fld.s
+# define FPR_S fst.s
+# define SZ_FPR 4
+#else
+# define SZ_FPR 0
+#endif
+
+#endif /* _LA_ASM_H */
diff --git a/libitm/config/loongarch/sjlj.S b/libitm/config/loongarch/sjlj.S
new file mode 100644
index 000000000..a5f9fadde
--- /dev/null
+++ b/libitm/config/loongarch/sjlj.S
@@ -0,0 +1,127 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ Contributed by Loongson Co. Ltd.
+
+ This file is part of the GNU Transactional Memory Library (libitm).
+
+ Libitm is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include "asmcfi.h"
+#include "asm.h"
+
+ .text
+ .align 2
+ .global _ITM_beginTransaction
+ .type _ITM_beginTransaction, @function
+
+_ITM_beginTransaction:
+ cfi_startproc
+ move $r5, $sp
+ ADDSP(-(12*SZ_GPR+8*SZ_FPR))
+ cfi_adjust_cfa_offset(12*SZ_GPR+8*SZ_FPR)
+
+ /* Frame Pointer */
+ GPR_S $fp, $sp, 0*SZ_GPR
+ cfi_rel_offset(22, 0)
+
+ /* Return Address */
+ GPR_S $r1, $sp, 1*SZ_GPR
+ cfi_rel_offset(1, SZ_GPR)
+
+ /* Caller's $sp */
+ GPR_S $r5, $sp, 2*SZ_GPR
+
+ /* Callee-saved scratch GPRs (r23-r31) */
+ GPR_S $s0, $sp, 3*SZ_GPR
+ GPR_S $s1, $sp, 4*SZ_GPR
+ GPR_S $s2, $sp, 5*SZ_GPR
+ GPR_S $s3, $sp, 6*SZ_GPR
+ GPR_S $s4, $sp, 7*SZ_GPR
+ GPR_S $s5, $sp, 8*SZ_GPR
+ GPR_S $s6, $sp, 9*SZ_GPR
+ GPR_S $s7, $sp, 10*SZ_GPR
+ GPR_S $s8, $sp, 11*SZ_GPR
+
+#if !defined(__loongarch_soft_float)
+ /* Callee-saved scratch FPRs (f24-f31) */
+ FPR_S $f24, $sp, 12*SZ_GPR + 0*SZ_FPR
+ FPR_S $f25, $sp, 12*SZ_GPR + 1*SZ_FPR
+ FPR_S $f26, $sp, 12*SZ_GPR + 2*SZ_FPR
+ FPR_S $f27, $sp, 12*SZ_GPR + 3*SZ_FPR
+ FPR_S $f28, $sp, 12*SZ_GPR + 4*SZ_FPR
+ FPR_S $f29, $sp, 12*SZ_GPR + 5*SZ_FPR
+ FPR_S $f30, $sp, 12*SZ_GPR + 6*SZ_FPR
+ FPR_S $f31, $sp, 12*SZ_GPR + 7*SZ_FPR
+#endif
+ move $fp, $sp
+
+ /* Invoke GTM_begin_transaction with the struct we've just built. */
+ move $r5, $sp
+ bl %plt(GTM_begin_transaction)
+
+ /* Return. (no call-saved scratch reg needs to be restored here) */
+ GPR_L $fp, $sp, 0*SZ_GPR
+ cfi_restore(22)
+ GPR_L $r1, $sp, 1*SZ_GPR
+ cfi_restore(1)
+
+ ADDSP(12*SZ_GPR+8*SZ_FPR)
+ cfi_adjust_cfa_offset(-(12*SZ_GPR+8*SZ_FPR))
+
+ jr $r1
+ cfi_endproc
+ .size _ITM_beginTransaction, . - _ITM_beginTransaction
+
+ .align 2
+ .global GTM_longjmp
+ .hidden GTM_longjmp
+ .type GTM_longjmp, @function
+
+GTM_longjmp:
+ cfi_startproc
+ GPR_L $s0, $r5, 3*SZ_GPR
+ GPR_L $s1, $r5, 4*SZ_GPR
+ GPR_L $s2, $r5, 5*SZ_GPR
+ GPR_L $s3, $r5, 6*SZ_GPR
+ GPR_L $s4, $r5, 7*SZ_GPR
+ GPR_L $s5, $r5, 8*SZ_GPR
+ GPR_L $s6, $r5, 9*SZ_GPR
+ GPR_L $s7, $r5, 10*SZ_GPR
+ GPR_L $s8, $r5, 11*SZ_GPR
+
+ FPR_L $f24, $r5, 12*SZ_GPR + 0*SZ_FPR
+ FPR_L $f25, $r5, 12*SZ_GPR + 1*SZ_FPR
+ FPR_L $f26, $r5, 12*SZ_GPR + 2*SZ_FPR
+ FPR_L $f27, $r5, 12*SZ_GPR + 3*SZ_FPR
+ FPR_L $f28, $r5, 12*SZ_GPR + 4*SZ_FPR
+ FPR_L $f29, $r5, 12*SZ_GPR + 5*SZ_FPR
+ FPR_L $f30, $r5, 12*SZ_GPR + 6*SZ_FPR
+ FPR_L $f31, $r5, 12*SZ_GPR + 7*SZ_FPR
+
+ GPR_L $r7, $r5, 2*SZ_GPR
+ GPR_L $fp, $r5, 0*SZ_GPR
+ GPR_L $r1, $r5, 1*SZ_GPR
+ cfi_def_cfa(5, 0)
+ move $sp, $r7
+ jr $r1
+ cfi_endproc
+ .size GTM_longjmp, . - GTM_longjmp
+
+#ifdef __linux__
+.section .note.GNU-stack, "", @progbits
+#endif
diff --git a/libitm/config/loongarch/target.h b/libitm/config/loongarch/target.h
new file mode 100644
index 000000000..0c5cf3ada
--- /dev/null
+++ b/libitm/config/loongarch/target.h
@@ -0,0 +1,50 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ Contributed by Loongson Co. Ltd.
+
+ This file is part of the GNU Transactional Memory Library (libitm).
+
+ Libitm is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+namespace GTM HIDDEN {
+
+typedef struct gtm_jmpbuf
+ {
+ long int fp; /* Frame Pointer: r22 */
+ long int pc; /* Return Address: r1 */
+ void *cfa; /* CFA: r3 */
+ long int gpr[9]; /* Callee-saved scratch GPRs: r23(s0)-r31(s8) */
+
+ /* Callee-saved scratch FPRs: f24-f31 */
+#if defined(__loongarch_double_float)
+ double fpr[8];
+#elif defined(__loongarch_single_float)
+ float fpr[8];
+#endif
+ } gtm_jmpbuf;
+
+#define HW_CACHELINE_SIZE 128
+
+static inline void
+cpu_relax (void)
+{
+ __asm__ volatile ("" : : : "memory");
+}
+
+} // namespace GTM
diff --git a/libitm/configure.tgt b/libitm/configure.tgt
index 06e90973e..4c0e78cff 100644
--- a/libitm/configure.tgt
+++ b/libitm/configure.tgt
@@ -80,6 +80,8 @@ EOF
ARCH=x86
;;
+ loongarch*) ARCH=loongarch ;;
+
sh*) ARCH=sh ;;
sparc)
--
2.33.0
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